( en | de | ru )

 

Disambiguation of "Kondo, Masaaki"

Author of the publication

copydeleteadd this publication to your clipboard
Scalable deep neural network accelerator cores with cubic integration using through chip interface.

, , , , , , , and . ISOCC, page 155-156. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Masaaki Minakawa

Masaaki Hayashida

Masaaki Tsukamoto

Katsuhiko Kondo

Kanjior Kondo

 

Other publications of authors with the same name

Generation High resolution 3D model from natural language by Generative Adversarial Network., , and . CoRR, (2019)Geyser., , , , , and . Handbook of Energy-Aware and Green Computing, Chapman and Hall/CRC, (2012)The Effectiveness of Low-Precision Floating Arithmetic on Numerical Codes: A Case Study on Power Consumption., , , , and . HPC Asia, page 199-206. ACM, (2020)A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface., , , , , , , , , and 1 other author(s). IEEE Micro, 33 (6): 6-15 (2013)A Scalable Body Bias Optimization Method Toward Low-Power CGRAs., , , and . IEEE Micro, 43 (1): 49-57 (2023)A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices., , and . IEEE Trans. Computers, 69 (7): 1027-1044 (2020)Enabling circuit-switching in modern on-chip networks., , , and . Microprocess. Microsystems, (November 2022)Quantum Circuit Fidelity Improvement with Long Short-Term Memory Networks., , and . CoRR, (2023)Evaluation of Performance and Power Consumption on Supercomputer Fugaku Using SPEC HPC Benchmarks., , and . IEICE Trans. Electron., 106 (6): 303-311 (June 2023)QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery., , , , and . HPCA, page 274-287. IEEE, (2022)