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Disambiguation of "Nakamura, Hiroshi"

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Scalable deep neural network accelerator cores with cubic integration using through chip interface.

, , , , , , , and . ISOCC, page 155-156. IEEE, (2017)

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Shin'ichiro Nakamura

Makoto Nakamura

Akira Nakamura

Hiroshi Kawabe

Hiroshi Murata

 

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Design and evaluation of fine-grained power-gating for embedded microprocessors., , , , , , , , , and 3 other author(s). DATE, page 1-6. European Design and Automation Association, (2014)Scenario Analysis for Clean Energy Vehicles in UK Considering Introduction of Renewable Energy Sources., and . IJAT, 11 (4): 592-600 (2017)Heart Rate and Heart Rate Variability Measuring System by Using Smartphone., , , , and . ACIT/CSII/BCD, page 47-52. IEEE, (2017)A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology., , , , , , , , , and 39 other author(s). IEEE J. Solid State Circuits, 55 (1): 178-188 (2020)Proposal of position sensorless control and torque ripple compensation based on torque sensor feedback., , , and . IECON, page 805-810. IEEE, (2014)Distinction of Heart Sound and Respiratory Sound Using Body Conduction Sound Sensor Based on HPSS., , , , , and . ACIT, page 31:1-31:6. ACM, (2019)A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory., , , , , , , , and . IEEE J. Solid State Circuits, 29 (11): 1366-1373 (November 1994)Circuit techniques for a 1.8-V-only NAND flash memory., , , and . IEEE J. Solid State Circuits, 37 (1): 84-89 (2002)A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 32 (5): 670-680 (1997)CP-PACS: A massively parallel processor at the University of Tsukuba., , , , and . Parallel Comput., 25 (13-14): 1635-1661 (1999)