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Disambiguation of "Joshi, Ajay"

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Subsetting the SPEC CPU2006 benchmark suite.

, , and . SIGARCH Comput. Archit. News, 35 (1): 69-76 (2007)

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Ajay Chavan

Godwin Olu Ajayi

Jidnyasa Joshi

Ajay Wakhloo

Ajay Moza

 

Other publications of authors with the same name

Sub-threshold logic circuit design using feedback equalization., and . DATE, page 1-6. European Design and Automation Association, (2014)Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)., and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 899-910 (2005)Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing., , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (9): 990-1002 (2007)Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization., and . IEEE Trans. Very Large Scale Integr. Syst., 24 (3): 884-896 (2016)Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes., , , and . ICICS, volume 5927 of Lecture Notes in Computer Science, page 47-62. Springer, (2009)Gate-Level Validation of Integrated Circuits With Structured-Illumination Read-Out of Embedded Optical Signatures., , , , , and . IEEE Access, (2020)Custom Tailored Suite of Random Forests for Prefetcher Adaptation., , , and . CoRR, (2020)Using GUI Design Theory to Develop an Open Source Touchscreen Smartphone GUI., and . Comput. Inf. Sci., 8 (2): 43-57 (2015)UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs., , , , , , , , and . ACM Trans. Archit. Code Optim., 13 (4): 35:1-35:25 (2016)Thermal management of manycore systems with silicon-photonic networks., , , and . DATE, page 1-6. European Design and Automation Association, (2014)