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Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI).

, and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 899-910 (2005)

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Impact of three-dimensional architectures on interconnects in gigascale integration., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 922-928 (2001)Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing., and . SoCC, page 137-142. IEEE, (2005)Designing for signal integrity in wave-pipelined SOC global interconnects., and . SoCC, page 207-210. IEEE, (2005)A priori prediction of tightly clustered connections based on heuristic classification trees., and . SLIP, page 9-15. ACM, (2006)Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures., , , and . SLIP, page 123-127. ACM, (2000)Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session)., , , and . SLIP, page 147-148. ACM, (2000)Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)., , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 899-912 (2001)A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI)., and . SLIP, page 64-68. ACM, (2004)Optimization of throughput performance for low-power VLSI interconnects., and . IEEE Trans. Very Large Scale Integr. Syst., 13 (3): 308-318 (2005)Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects., and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (4): 1023-1030 (2008)