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Layerweaver+: A QoS-Aware Layer-Wise DNN Scheduler for Multi-Tenant Neural Processing Units.

, , , and . IEICE Trans. Inf. Syst., 105-D (2): 427-431 (2022)

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Layerweaver: Maximizing Resource Utilization of Neural Processing Units via Layer-Wise Scheduling., , , , , , , , , and . HPCA, page 584-597. IEEE, (2021)An eDRAM-Based Approximate Register File for GPUs., , , and . IEEE Des. Test, 33 (1): 23-31 (2016)eDRAM-based tiered-reliability memory with applications to low-power frame buffers., , , , and . ISLPED, page 333-338. ACM, (2014)A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (9): 3228-3232 (September 2023)An 8-bit Ring-Amplifier Based Mixed-Signal MAC Circuit With Full Digital Interface and Variable Accumulation Length., , , , , and . IEEE Access, (2021)Typed Architectures: Architectural Support for Lightweight Scripting., , , , , , , , and . ASPLOS, page 77-90. ACM, (2017)Layerweaver+: A QoS-Aware Layer-Wise DNN Scheduler for Multi-Tenant Neural Processing Units., , , and . IEICE Trans. Inf. Syst., 105-D (2): 427-431 (2022)Genesis: A Hardware Acceleration Framework for Genomic Data Analysis., , , , , , , , , and . ISCA, page 254-267. IEEE, (2020)Short-Circuit Dispatch: Accelerating Virtual Machine Interpreters on Embedded Processors., , , , , , , and . ISCA, page 291-303. IEEE Computer Society, (2016)Developing Automated Input Generator for Android Mobile Device to Evaluate Malware Behavior., , and . RIIT, page 43. ACM, (2015)