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Другие публикации лиц с тем же именем

Generation of optimal code for expressions via factorization.. Commun. ACM, 12 (6): 333-340 (1969)A Test and Maintenance Controller for a Module Containing Testable Chips., и . ITC, стр. 502-513. IEEE Computer Society, (1988)Built-in test for folded programmable logic arrays., и . Microprocess. Microsystems, 11 (6): 319-329 (1987)Functional Partitioning and Simulation of Digital Circuits.. IEEE Trans. Computers, 19 (11): 1038-1046 (1970)A Note on Three-Valued Logic Simulation.. IEEE Trans. Computers, 21 (4): 399-402 (1972)Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (5): 754-764 (2012)Test Schedules for VLSI Circuits Having Built-In Test Hardware., и . IEEE Trans. Computers, 35 (4): 361-367 (1986)On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays., и . IEEE Trans. Computers, 33 (1): 21-27 (1984)Procedures for Eliminating Static and Dynamic Hazards in Test Generation., и . IEEE Trans. Computers, 23 (10): 1069-1078 (1974)Roving Emulation as a Fault Detection Mechanism., и . IEEE Trans. Computers, 35 (11): 933-939 (1986)