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A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications.

, , , , , and . ICFPT, page 298-299. IEEE, (2023)

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HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (3): 505-518 (March 2024)A High-performance Open-channel Open-way NAND Flash Controller Architecture., , and . FPL, page 91-98. IEEE, (2021)High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator., , , , and . FPT, page 290-291. IEEE, (2020)An Automatic Optimization Method of Combinational Logic Loops in CGRA., , , and . ASICON, page 1-4. IEEE, (2023)TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework., , , , and . FPL, page 61-69. IEEE, (2022)PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design., , , , , , , and . FCCM, page 226. IEEE, (2023)FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism., , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 17 (1): 4:1-4:26 (March 2024)E2-ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End Toolchain., , , , , and . ICFPT, page 296-297. IEEE, (2023)FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA., , , , , , , , , and 1 other author(s). IEEE Trans. Parallel Distributed Syst., 31 (8): 1828-1444 (2020)A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications., , , , , and . ICFPT, page 298-299. IEEE, (2023)