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13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process., , , , , , , , , and 27 other author(s). ISSCC, page 234-236. IEEE, (2024)Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product., , , , , , , , , and 6 other author(s). ISCA, page 43-56. IEEE, (2021)Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices., , , , , , , , , and 2 other author(s). HPCA, page 61-72. IEEE Computer Society, (2017)McDRAM v2: In-Dynamic Random Access Memory Systolic Array Accelerator to Address the Large Model Problem in Deep Neural Networks on the Edge., , , , and . IEEE Access, (2020)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond., , , , , , , , , and 10 other author(s). HCS, page 1-26. IEEE, (2021)McDRAM: Low Latency and Energy-Efficient Matrix Computations in DRAM., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (11): 2613-2622 (2018)Main Memory in HPC: Do We Need More or Could We Live with Less?, , , , , , , , and . ACM Trans. Archit. Code Optim., 14 (1): 3:1-3:26 (2017)25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications., , , , , , , , , and 20 other author(s). ISSCC, page 350-352. IEEE, (2021)