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Disambiguation of "Paschalis, Antonis M."

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Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors.

, , , and . IEEE Trans. Computers, 58 (12): 1682-1694 (2009)

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Eustratios Paschalis

Paschalis Tossios

Paschalis Papanikolaou

Antonis Papapantoleon

Antonis Tsiongas

 

Other publications of authors with the same name

Power-aware optimization of software-based self-test for L1 caches in microprocessors., , , and . IOLTS, page 154-159. IEEE, (2014)Efficient Architectures for Multigigabit CCSDS LDPC Encoders., , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (5): 1118-1127 (2020)Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units., , , and . IEEE Trans. Dependable Secur. Comput., 6 (2): 124-134 (2009)Hybrid-SBST Methodology for Efficient Testing of Processor Cores., , , , and . IEEE Des. Test Comput., 25 (1): 64-75 (2008)Accumulator Based 3-Weight Pattern Generation., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 357-361 (2012)A concurrent built-in self-test architecture based on a self-testing RAM., , , , and . IEEE Trans. Reliab., 54 (1): 69-78 (2005)Efficient Totally Self-Checking Checkers for a Class of Borden Codes., , and . IEEE Trans. Computers, 44 (11): 1318-1322 (1995)An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set., , , , , and . IEEE Trans. Computers, 57 (8): 1012-1022 (2008)A Totally Self-Checking 1-out-of-3 Code Error Indicator., , , and . J. Electron. Test., 13 (1): 61-66 (1998)An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology., , , , and . CoRR, (2022)