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FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs.

, , , , and . FPGA, page 15-25. ACM, (2023)

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The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models., , , , , , , , , and 24 other author(s). CoRR, (2024)RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model., , , and . CoRR, (2023)RouteNet: routability prediction for mixed-size designs using convolutional neural network., , , , , , and . ICCAD, page 80. ACM, (2018)Robustify ML-Based Lithography Hotspot Detectors., , , , and . ICCAD, page 134:1-134:7. ACM, (2022)Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization., , , and . CoRR, (2024)Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS., , , and . CoRR, (2024)CAMU-Net: Copy-move forgery detection utilizing coordinate attention and multi-scale feature fusion-based up-sampling., , , , , , and . Expert Syst. Appl., 238 (Part C): 121918 (March 2024)AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs., , , , , , and . CoRR, (2024)Fast IR Drop Estimation with Machine Learning., , , , and . CoRR, (2020)The Dark Side: Security Concerns in Machine Learning for EDA., , , and . CoRR, (2022)