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Data flow analysis from UML/MARTE models based on binary traces.

, , и . DCIS, стр. 1-6. IEEE, (2020)

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Eugenio Rivera

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Eugenio Amato

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Nicolas Villar

 

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Specification of Adaptive HW/SW Systems in SystemC., , и . FDL, стр. 61-65. IEEE, (2008)System Specification Experiments on a Common Benchmark., , , и . IEEE Des. Test Comput., 17 (3): 22-32 (2000)An algorithm for clock cycle selection in behavioral synthesis., , и . J. Syst. Archit., 44 (9-10): 773-786 (1998)A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design., , , , , , , и . J. Low Power Electron., 7 (1): 2-16 (2011)High-level modeling and exploration of a powerline communication network based on System-on-Chip., , , и . Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, Springer, (2011)POSIX modeling in SystemC., , , , и . ASP-DAC, стр. 485-490. IEEE, (2006)Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation., , , и . Microelectron. J., 45 (10): 1281-1291 (2014)Modeling and Performance Estimation of Robotic Systems using ROS: Application to drone-based Services., , , и . FDL, стр. 1-8. IEEE, (2021)Systemc refinement of abstract adaptive processes for implementation into Dynamically Reconfigurable Hardware., , и . FDL, стр. 1-8. IEEE, (2011)AADL Simulation and Performance Analysis in SystemC., и . ICECCS, стр. 323-328. IEEE Computer Society, (2009)