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Disambiguation of "Choo, Min-Seong"

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Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application.

, , and . ICEIC, page 1-2. IEEE, (2024)

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Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

Prem Choontanom

 

Other publications of authors with the same name

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop., , , , and . A-SSCC, page 73-76. IEEE, (2018)A theoretical analysis of phase shift in pulse injection-locked oscillators., , , , , and . ISCAS, page 1662-1665. IEEE, (2016)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology., , , , , and . IEEE J. Solid State Circuits, 54 (10): 2812-2822 (2019)An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (12): 1819-1823 (2018)An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies., , , and . IEEE Access, (2023)An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery., , , and . ICEIC, page 1-4. IEEE, (2024)Radiation-Hardened Processing-In-Memory Crossbar Array With Hybrid Synapse Devices for Space Application., , and . ICEIC, page 1-4. IEEE, (2023)A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection., , , , , , , , , and . ESSCIRC, page 384-387. IEEE, (2015)A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS., , , , , , and . VLSI Circuits, page 194-. IEEE, (2019)A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2691-2702 (2018)