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11.1 AMD InstinctTM MI300 Series Modular Chiplet Package - HPC and AI Accelerator for Exa-Class Systems.

, , , , , , , , , and . ISSCC, page 490-492. IEEE, (2024)

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A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 40 (1): 52-59 (2005)4.8 A 28nm x86 APU optimized for power and area efficiency., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU., , , , , , , , , and 4 other author(s). ISSCC, page 78-80. IEEE, (2011)Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 164-176 (2012)A third-generation SPARC V9 64-b microprocessor., , , , , , , , , and 21 other author(s). IEEE J. Solid State Circuits, 35 (11): 1526-1538 (2000)Carrizo: A High Performance, Energy Efficient 28 nm APU., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 51 (1): 105-116 (2016)11.1 AMD InstinctTM MI300 Series Modular Chiplet Package - HPC and AI Accelerator for Exa-Class Systems., , , , , , , , , and . ISSCC, page 490-492. IEEE, (2024)3.2 Zen: A next-generation high-performance ×86 core., , , , , , , , , and 3 other author(s). ISSCC, page 52-53. IEEE, (2017)