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Disambiguation of "Chen, Mark"

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Mapping the learning pathways and processes associated with the development of expertise and learner identities.

, , , , , , , , , , , , , , , , , , and . ICLS (3), page 206-213. International Society of the Learning Sciences, (2008)

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Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

 

Other publications of authors with the same name

Addressing social dilemmas and fostering cooperation through computer games.. DiGRA Conference, (2005)Engineering Multifunctional Biologically-Amenable Nanomaterials for Interfacial Therapeutic Delivery and Substrate-Based Cellular Interrogation., , , , , , and . BIBE, page 517-523. IEEE Computer Society, (2007)A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation., , , , , , and . IEEE J. Solid State Circuits, 54 (7): 2028-2037 (2019)Training Verifiers to Solve Math Word Problems., , , , , , , , , and 2 other author(s). CoRR, (2021)Scaling Laws for Autoregressive Generative Modeling., , , , , , , , , and 9 other author(s). CoRR, (2020)When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA., , , , , , and . DAC, page 1-6. IEEE, (2023)A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS., , , , , , , , , and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Development of a Low Cost 15-Gsps Analog-to-Digital Converter Board by using a Field Programmable Gate Array Mezzanine Card Connector for FPGA-Based Backends., , , and . ISIE, page 1345-1350. IEEE, (2019)Protocol Failures Related to Order of Encryption and Signature., and . ACISP, volume 1438 of Lecture Notes in Computer Science, page 238-249. Springer, (1998)Modeling and Measuring Engagement in Computer Games., , , and . DiGRA Conference, (2005)