( en | de | ru )

 

Disambiguation of "Riener, Heinz"

Author of the publication

copydeleteadd this publication to your clipboard
Logic Optimization of Majority-Inverter Graphs.

, , , , , , and . MBMV, page 1-4. VDE Verlag, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Cordian Riener

Robert Riener

Isabella Riener

Robert Riener

Robert Riener

 

Other publications of authors with the same name

Simulation-Guided Boolean Resubstitution., , , , and . CoRR, (2020)Evaluating ESOP Optimization Methods in Quantum Compilation Flows., , , , and . RC, volume 11497 of Lecture Notes in Computer Science, page 191-206. Springer, (2019)Design Understanding: From Logic to Specification*., , , , , and . VLSI-SoC, page 172-175. IEEE, (2018)Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies., , , and . DATE, page 354-359. IEEE, (2021)Formal methods for automated debugging.. University of Bremen, Germany, (2017)Scalable Generic Logic Synthesis: One Approach to Rule Them All., , , , , , and . DAC, page 70. ACM, (2019)Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle., , and . DATE, page 738-743. IEEE, (2020)Safety Synthesis Sans Specification., , , , and . CoRR, (2020)On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis., , , , and . DATE, page 1649-1654. IEEE, (2019)Three-Input Gates for Logic Synthesis., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)