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Circuit design of a dual-versioning L1 data cache., , , , , and . Integr., 45 (3): 237-245 (2012)RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors., , , and . IEEE Comput. Archit. Lett., 20 (1): 78-81 (2021)Breaking In-Order Branch Miss Recovery., , , and . IEEE Comput. Archit. Lett., 19 (1): 30-33 (2020)The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor., , , , , , , , , and 10 other author(s). IEEE Micro, 43 (5): 78-87 (September 2023)Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study., and . CoRR, (2022)Many-core graph workload analysis., , , , and . SC, page 22:1-22:11. IEEE / ACM, (2018)Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation., , , and . ISPASS, page 124-133. IEEE, (2023)Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory., , , , , , and . PACT, page 361-371. IEEE Computer Society, (2011)STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems., , , , , , and . PACT, page 221-231. IEEE Computer Society, (2011)Circuit design of a dual-versioning L1 data cache for optimistic concurrency., , , , , and . ACM Great Lakes Symposium on VLSI, page 325-330. ACM, (2011)