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A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing.

, , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (2): 329-340 (2018)

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X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators., , , , and . CoRR, (2024)A multi-Gbps unrolled hardware list decoder for a systematic polar code., , , , , and . ACSSC, page 1194-1198. IEEE, (2016)X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller., , , , , , , , and . CF, page 379-380. ACM, (2023)A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2019)A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (2): 329-340 (2018)A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code., , , , , and . CoRR, (2017)PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes., , , , , , , and . CoRR, (2017)Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC., , , , , , , , and . PRIME, page 285-288. IEEE, (2019)A 594 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing., , , , , , and . CoRR, (2017)A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors., , , , , , , and . IEEE Des. Test, 34 (6): 46-53 (2017)