( en | de | ru )

 

Disambiguation of "Yin, Shihui"

Author of the publication

copydeleteadd this publication to your clipboard
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning.

, , , , , , , , , and . IEEE Micro, 39 (6): 54-63 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shihui Li

Shihui Wang

Lu Yin

Renfu Yin

Li Yin

 

Other publications of authors with the same name

Phase Noise Impairment and Environment-Adaptable Fast (EAF) Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers., , , , , , and . GLOBECOM, page 1-6. IEEE, (2015)Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression., , , , , and . CoRR, (2018)Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration., , , , , and . ACSSC, page 1516-1521. IEEE, (2019)K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM., , , , and . ISLPED, page 1-6. IEEE, (2019)Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection., , , , , , and . IEEE Des. Test, 39 (4): 71-80 (2022)PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference., , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability., , , , , , , , , and 7 other author(s). VLSI Technology and Circuits, page 300-301. IEEE, (2022)Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data., , , , , , and . ASP-DAC, page 441-446. IEEE, (2015)XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks., , , and . IEEE J. Solid State Circuits, 55 (6): 1733-1743 (2020)Energy-Efficient Circuit and Architecture Designs for Intelligent Systems.. Arizona State University, Tempe, USA, (2020)base-search.net (ftarizonastateun:item:62917).