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Racetrack memory-based encoder/decoder for low-power interconnect architectures.

S. Deb, L. Ni, H. Yu, and A. Chattopadhyay. SAMOS, page 281-287. IEEE, (2016)

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Ying Ni

Pedestrian safety at urban signalised intersectionsY. Ni. TU Darmstadt, (2009)

Yi Ni

Ji Ni

Xiaoju Ni

Jianbing Ni

Other publications of authors with the same name

A 3D multi-layer CMOS-RRAM accelerator for neural network.H. Huang, L. Ni, Y. Wang, H. Yu, Z. Wang, Y. Cai, and R. Huang. 3DIC, page 1-5. IEEE, (2016)An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar.L. Ni, Z. Liu, W. Song, J. Yang, H. Yu, K. Wang, and Y. Wang. ISLPED, page 1-6. IEEE, (2017)A memristor network with coupled oscillator and crossbar towards L2-norm based machine learning.L. Ni, H. Huang, and H. Yu. NANOARCH, page 179-184. ACM, (2016)Machine learning based soft error rate estimation of pass transistor logic in high-speed communication.Z. Zhang, J. Lappas, A. Chinazzo, C. Weis, Z. Wu, L. Ni, N. Wehn, and M. Tahoori. ETS, page 1-4. IEEE, (2022)Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology.A. Chinazzo, J. Lappas, C. Weis, Q. Huang, Z. Wu, L. Ni, and N. Wehn. ICECS 2022, page 1-4. IEEE, (2022)A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error Compensation.L. Du, L. Ni, X. Liu, W. Mao, and H. Yu. APCCAS, page 226-230. IEEE, (2022)AFPR-CIM: An Analog-Domain Floating-Point RRAM-based Compute-In-Memory Architecture with Dynamic Range Adaptive FP-ADC.H. Liu, Z. Qian, W. Wu, H. Ren, Z. Liu, and L. Ni. CoRR, (2024)Distributed In-Memory Computing on Binary RRAM Crossbar.L. Ni, H. Huang, Z. Liu, R. Joshi, and H. Yu. JETC, 13 (3): 36:1-36:18 (2017)Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node.J. Lappas, A. Chinazzo, C. Weis, C. Xia, Z. Wu, L. Ni, and N. Wehn. DATE, page 1083-1084. IEEE, (2022)DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory.Y. Wang, L. Ni, C. Chang, and H. Yu. IEEE Trans. Inf. Forensics Secur., 11 (11): 2426-2440 (2016)

BibSonomy

Disambiguation of "Ni, Leibin"

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Racetrack memory-based encoder/decoder for low-power interconnect architectures.

Please choose a person to relate this publication to

Ying Ni

Yi Ni

Ji Ni

Xiaoju Ni

Jianbing Ni

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ni, Leibin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Racetrack memory-based encoder/decoder for low-power interconnect architectures.

Please choose a person to relate this publication to

Ying Ni

Yi Ni

Ji Ni

Xiaoju Ni

Jianbing Ni

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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Racetrack memory-based encoder/decoder for low-power interconnect architectures.