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Disambiguation of "Sundareswaran, Savithri"

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On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.

, , , , , , , and . DAC, page 162-167. IEEE, (2007)

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Other publications of authors with the same name

SLECTS: Slew-Driven Clock Tree Synthesis., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 864-874 (2019)An Assertion Based Technique for Transistor Level Dynamic Power Estimation., , and . VLSI Design, page 34-37. IEEE Computer Society, (2000)A novel technique for incremental analysis of on-chip power distribution networks., , , , and . ICCAD, page 817-823. IEEE Computer Society, (2007)A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming., , , , and . DAC, page 217-222. ACM, (2006)Faster statistical cell characterization using adjoint sensitivity analysis., , , and . CICC, page 229-232. IEEE, (2008)Small-Delay Defect Detection in the Presence of Process Variations., , and . ISQED, page 711-716. IEEE Computer Society, (2007)Vectorless Analysis of Supply Noise Induced Delay Variation., , , , and . ICCAD, page 184-192. IEEE Computer Society / ACM, (2003)Impact of Low-Impedance Substrate on Power Supply Integrity., , and . IEEE Des. Test Comput., 20 (3): 16-22 (2003)Total sensitivity based dfm optimization of standard library cells., , and . ISPD, page 113-120. ACM, (2010)Characterization of sequential cells for constraint sensitivities., , , , and . ISQED, page 74-79. IEEE Computer Society, (2009)