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Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (7): 1201-1210 (2012)Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 335-342 (2011)Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling., , , , and . ISCAS, page 1130-1133. IEEE, (2014)Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell., , , , and . ISLPED, page 255-258. ACM, (2014)A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance., , , , , , and . ESSDERC, page 157-160. IEEE, (2012)Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (12): 3339-3347 (2014)Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells., , , and . ISCAS, page 601-604. IEEE, (2015)Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness., , , , , and . ISCAS, page 2325-2328. IEEE, (2015)Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 4 (4): 389-399 (2014)Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits., , , , , and . ICICDT, page 61-64. IEEE, (2013)