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Disambiguation of "Geurts, Werner"

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Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization.

, , , and . EDAC-ETC-EUROASIC, page 490-494. IEEE Computer Society, (1994)

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Jean Geurts

Heinrich Geurts

Jean Geurts

Petra Geurts

Hans Geurts

 

Other publications of authors with the same name

Quadratic zero-one programming-based synthesis of application-specific data paths., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (1): 1-11 (1995)Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization., , , and . EDAC-ETC-EUROASIC, page 490-494. IEEE Computer Society, (1994)Processor modeling and code selection for retargetable compilation., , , and . ACM Trans. Design Autom. Electr. Syst., 6 (3): 277-307 (2001)Quadratic zero-one programming based synthesis of application specific data paths., , and . ICCAD, page 522-525. IEEE Computer Society / ACM, (1993)Testability analysis in high level data path synthesis., , , and . J. Electron. Test., 4 (1): 43-56 (1993)ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces., , , , , , , , , and 2 other author(s). Future Gener. Comput. Syst., (2015)Loop transformation methodology for fixed-rate video, image and telecom processing applications., , and . ASAP, page 427-438. IEEE, (1994)Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications., , , and . DAC, page 597-602. ACM, (1991)Chess: retargetable code generation for embedded DSP processors., , , , , , and . Code Generation for Embedded Processors, page 85-102. Kluwer, (1994)Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications., , , and . VLSI, volume A-1 of IFIP Transactions, page 193-202. North-Holland, (1991)