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Disambiguation of "Dosho, Shiro"

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A time-domain architecture and design method of high speed A-to-D converters with standard cells.

, , , , and . A-SSCC, page 353-356. IEEE, (2011)

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Shiro Kobayashi

Shiro Takebayashi

Shiro Kobayashi

Shiro Yukawa

Shiro Ando

 

Other publications of authors with the same name

A 0.03mm2 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface., , , , and . ISSCC, page 1286-1295. IEEE, (2006)A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise., , , , , , , and . ISSCC, page 272-273. IEEE, (2013)Continuous-Time Delta-Sigma Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey.. IEICE Trans. Electron., 95-C (6): 978-998 (2012)Foreword.. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (2): 429 (2012)Digital Calibration and Correction Methods for CMOS Analog-to-Digital Converters.. IEICE Trans. Electron., 95-C (4): 421-431 (2012)A time-domain architecture and design method of high speed A-to-D converters with standard cells., , , , and . A-SSCC, page 353-356. IEEE, (2011)Design methods for pipeline & delta-sigma A-to-D converters with convex optimization., , , , , , , , , and . ASP-DAC, page 690-695. IEEE, (2009)A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver., , , , , , and . CICC, page 1-4. IEEE, (2010)A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process., , and . IEEE J. Solid State Circuits, 37 (5): 559-565 (2002)Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique., , , , , , , , , and 3 other author(s). ASP-DAC, page 43-44. IEEE, (2017)