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Understanding the Effect of Process Variations on the Delay of Static and Domino Logic., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 697-710 (2010)Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity., , and . ICECS, page 155-158. IEEE, (2009)Modeling of Feedback Analog Circuits with VHDL., , , and . ICECS, page 882-885. IEEE, (2006)Analysis of the impact of random process variations in CMOS tapered buffers., , and . ICECS, page 57-60. IEEE, (2009)Analysis of the impact of process variations on static logic circuits versus fan-in., , and . ICECS, page 137-140. IEEE, (2008)Behavioral model of charge pumps with VHDL., , and . ICECS, page 1-4. IEEE, (2005)Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 284-295 (2012)Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits., , , and . ECCTD, page 779-782. IEEE, (2009)Miller Theorem for Weakly Nonlinear Feedback Circuits and Application to CE Amplifier., , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (10): 991-995 (2008)Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic., , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 136-145. Springer, (2008)