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Disambiguation of "Kwon, Dae-Han"

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A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer.

, , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)

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Dae-Joong Kwon

Jeong Dae Han

Dae-Ho Cho

Hyogmyon Kwon

Jagun Kwon

 

Other publications of authors with the same name

A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface., , , , , , , , , and 1 other author(s). ISSCC, page 48-50. IEEE, (2012)A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application., , , , , , , , , and 27 other author(s). IEEE J. Solid State Circuits, 58 (1): 291-302 (2023)A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 814-818 (2022)A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer., , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications., , , , , , , , , and 11 other author(s). ISSCC, page 210-212. IEEE, (2018)A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer., , , , , , , and . IEEE J. Solid State Circuits, 57 (10): 3083-3093 (2022)A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface., , , , , , , , , and . IEEE J. Solid State Circuits, 51 (8): 1890-1901 (2016)A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications., , , , , , , , , and 21 other author(s). ISSCC, page 1-3. IEEE, (2022)