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Disambiguation of "Chattopadhyay, Saranyu"

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Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition.

, , , , , , , , , , , , , , and . FMCAD, page 42-52. IEEE, (2021)

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Anupam Chattopadhyay

Dhrupadi Chattopadhyay

Shamita Chattopadhyay

Renate Chattopadhyay

Sibylle Chattopadhyay

 

Other publications of authors with the same name

LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (4): 854-867 (2022)A-QED Verification of Hardware Accelerators., , , , , , , , , and 3 other author(s). DAC, page 1-6. IEEE, (2020)G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators., , , , , , , , , and 2 other author(s). DAC, page 1-6. IEEE, (2023)Cyclic Beneš Network Based Logic Encryption for Mitigating SAT-Based Attacks., and . ICCD, page 567-575. IEEE, (2019)Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory Detection., , , and . ATS, page 49-54. IEEE, (2019)A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability., , , , and . ACM Trans. Design Autom. Electr. Syst., 26 (6): 41:1-41:24 (2021)A novel technique for implementing reactance in spin domain using Spin Hall Effect.. Microelectron. J., (2018)STT-MRAM for Low Power Access for Read-Intensive Parallel Deep-Learning Architectures., , , and . iNIS, page 61-65. IEEE, (2017)Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition., , , , , , , , , and 5 other author(s). FMCAD, page 42-52. IEEE, (2021)Proof-Stitch: Proof Combination for Divide-and-Conquer SAT Solvers., , , , and . FMCAD, page 84-88. IEEE, (2022)