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Disambiguation of "Alioto, Massimo"

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Design of MUX, XOR and D-latch SCL gates.

, and . ISCAS (5), page 261-264. IEEE, (2003)

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Massimo Viola

Massimo Tallarida

Massimo Malagó

Massimo Moser

Massimo Busin

 

Other publications of authors with the same name

A gate-level strategy to design Carry Select Adders., , and . ISCAS (2), page 465-468. IEEE, (2004)A general model for differential power analysis attacks to static logic circuits., , and . ISCAS, page 3346-3349. IEEE, (2008)Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits., , and . ISCAS, page 3150-3153. IEEE, (2009)26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage., , and . ISSCC, page 440-441. IEEE, (2017)EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS., , and . A-SSCC, page 241-244. IEEE, (2017)Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems., , , and . CICC, page 1-4. IEEE, (2012)Performance evaluation of the low-voltage CML D-latch topology., , and . Integr., 36 (4): 191-209 (2003)Analysis and comparison on full adder block in submicron technology., and . IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 806-823 (2002)Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (5): 725-736 (2011)Comparative soft error evaluation of layout cells in FinFET technology., , and . Microelectron. Reliab., 54 (9-10): 2300-2305 (2014)