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Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method.

, , , and . Asian Test Symposium, page 354-359. IEEE Computer Society, (2003)

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Buffer insertion in large circuits with constructive solution search techniques., , and . DAC, page 296-301. ACM, (2006)Layout Capacitance Extraction Using Automatic Pre-Characterization and Machine Learning., and . ISQED, page 457-464. IEEE, (2020)Sparse transformations and preconditioners for 3-D capacitance extraction., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (9): 1420-1426 (2005)Path-Based Buffer Insertion., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (7): 1346-1355 (2007)Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2282-2286 (2006)Power Allocation for IRS-Aided Two-Way Decode-and-Forward Relay Wireless Network., , , , and . IEEE Trans. Veh. Technol., 72 (1): 1337-1342 (2023)A General Method to Design and Reconfigure Loop-Based Linear Arrays.. DFT, page 221-229. IEEE Computer Society, (1994)Numerical simulation of viscous flow over non-smooth surfaces., , and . Comput. Math. Appl., 61 (12): 3703-3710 (2011)Beamforming and Transmit Power Design for Intelligent Reconfigurable Surface-Aided Secure Spatial Modulation., , , , , , , and . IEEE J. Sel. Top. Signal Process., 16 (5): 933-949 (2022)Beamforming Design for IRS-aided Decode-and-Forward Relay Wireless Network., , , , , , and . CoRR, (2021)