Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS.

C. Chan, Y. Zhu, U. Chio, S. Sin, S. U, and R. Martins. A-SSCC, page 233-236. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hannelore Chiout

Lucia Chiovenda

Emmanouil Chiou

Marco Chiodi

Uta Chiodi-Tischer

Other publications of authors with the same name

A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.H. Wei, U. Chio, Y. Zhu, S. Sin, S. U, and R. da Silva Martins. APCCAS, page 1192-1195. IEEE, (2008)An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications.G. Yin, U. Chio, H. Wei, S. Sin, S. U., R. Martins, and Z. Wang. ICECS, page 878-881. IEEE, (2010)A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS.W. Wu, Y. Zhu, L. Ding, C. Chan, U. Chio, S. Sin, S. U., and R. Martins. ISCAS, page 2239-2242. IEEE, (2013)An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC.H. Wei, C. Chan, U. Chio, S. Sin, S. U., R. Martins, and F. Maloberti. IEEE J. Solid State Circuits, 47 (11): 2763-2772 (2012)A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method.T. Lee, T. Tsai, W. Lin, U. Chio, and C. Wang. IEEE Trans. Circuits Syst. II Express Briefs, 66-II (1): 116-120 (2019)A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS.G. Yin, H. Wei, U. Chio, S. Sin, S. U., Z. Wang, and R. Martins. ESSCIRC, page 377-380. IEEE, (2012)A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs.Y. Zhu, C. Chan, U. Chio, S. Sin, S. U., and R. Martins. ISCAS, page 4061-4064. IEEE, (2010)A C-less ASK demodulator for implantable neural interfacing chips.C. Wang, Y. Hsueh, U. Chio, and Y. Hsiao. ISCAS (4), page 57-60. IEEE, (2004)A power-efficient capacitor structure for high-speed charge recycling SAR ADCs.Y. Zhu, U. Chio, H. Wei, S. Sin, S. U., and R. Martins. ICECS, page 642-645. IEEE, (2008)A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier.H. Wei, U. Chio, S. Sin, S. U., and R. Martins. ISCAS, page 5-8. IEEE, (2008)

BibSonomy

Disambiguation of "Chio, U. Fat"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS.

Please choose a person to relate this publication to

Hannelore Chiout

Lucia Chiovenda

Emmanouil Chiou

Marco Chiodi

Uta Chiodi-Tischer

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chio, U. Fat"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS.

Please choose a person to relate this publication to

Hannelore Chiout

Lucia Chiovenda

Emmanouil Chiou

Marco Chiodi

Uta Chiodi-Tischer

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS.