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Disambiguation of "Lam, Tak-Kei"

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On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield.

, , , , and . ACM Great Lakes Symposium on VLSI, page 233-234. ACM, (2014)

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Kei Yoshimoto

Kei Ishii

Jaetaek Tak

Cindy Lam

Lam Tang

 

Other publications of authors with the same name

On applying erroneous clock gating conditions to further cut down power., , , and . ASP-DAC, page 509-514. IEEE, (2011)Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates)., , , and . ASP-DAC, page 139-146. IEEE, (2016)A coupling area reduction technique applying ODC shifting., , , and . DATE, page 1461-1466. ACM, (2015)A universal macro block mapping scheme for arithmetic circuits., , , and . DATE, page 1629-1634. ACM, (2015)Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire., , , , , and . VLSID, page 375-380. IEEE Computer Society, (2014)Almost every wire is removable: A modeling and solution for removing any circuit wire., , , and . DATE, page 1573-1578. IEEE, (2012)Logic synthesis for low power using clock gating and rewiring., , , and . ACM Great Lakes Symposium on VLSI, page 179-184. ACM, (2010)On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield., , , , and . ACM Great Lakes Symposium on VLSI, page 233-234. ACM, (2014)ECR: a low complexity generalized error cancellation rewiring scheme., , and . DAC, page 511-516. ACM, (2010)ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme., , , and . ACM Trans. Design Autom. Electr. Syst., 17 (4): 50:1-50:21 (2012)