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Disambiguation of "Hoe, James C."

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Fast and accurate resource estimation of automatically generated custom DFT IP cores

, , , and . Proceedings of the International Symposium on Field Programmable Gate Arrays, page 211--220. New York, NY, USA, ACM Press, (2006)
DOI: http://doi.acm.org/10.1145/1117201.1117232

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James C Cornette

James C Russell

Rudolf Hoé

Michael James

Audrein James

 

Other publications of authors with the same name

Time-Shared Execution of Realtime Streaming Pipelines by Dynamic Partial Reconfiguration., and . CoRR, (2018)A Service-Oriented Memory Architecture for FPGA Computing., and . FPL, page 91-97. IEEE, (2020)SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture., , , , , , , , and . SIGMETRICS Perform. Evaluation Rev., 31 (4): 31-34 (2004)Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA., , , , , and . IEEE Trans. Computers, 72 (5): 1343-1355 (May 2023)A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem., , , , , , , , , and . CoRR, (2021)Dual use of superscalar datapath for transient-fault detection and recovery., , and . MICRO, page 214-224. ACM/IEEE Computer Society, (2001)Operation-centric hardware description and synthesis.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2000)ndltd.org (oai:dspace.mit.edu:1721.1/86439).Synthesis of Operation-Centric Hardware Descriptions., and . ICCAD, page 511-518. IEEE Computer Society, (2000)Fast bilateral filtering by adapting block size., , , , and . ICIP, page 3281-3284. IEEE, (2010)Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration., and . FPL, page 230-234. IEEE Computer Society, (2018)