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A novel scheme to reduce power supply noise for high-quality at-speed scan testing.

, , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2007)

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A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Des. Test Comput., 26 (1): 26-35 (2009)Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing., , and . ACM Trans. Design Autom. Electr. Syst., 17 (2): 18:1-18:24 (2012)Self-Testing of Embedded RAMs., and . ITC, page 148-156. IEEE Computer Society, (1984)Low-capture-power test generation for scan-based at-speed testing., , , , , , and . ITC, page 10. IEEE Computer Society, (2005)CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing., , , , , , , and . ATS, page 397-402. IEEE Computer Society, (2008)At-Speed Logic BIST for IP Cores., , , , , , , , and . DATE, page 860-861. IEEE Computer Society, (2005)Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique., and . IEEE Trans. Computers, 35 (4): 367-370 (1986)GPU-based timing-aware test generation for small delay defects., , , , , and . ETS, page 1-2. IEEE, (2014)LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing., , , , , and . IEEE Des. Test, 30 (4): 60-70 (2013)