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Athena: An Early-Fetch Architecture to Reduce on-Chip Page Walk Latencies.

S. Vakil-Ghahani, S. Khadirsharbiyani, J. Kotra, and M. Kandemir. PACT, page 359-371. ACM, (2022)

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Jagadish Mudiganti

Jagadish Kulkarni

Jagadish Ghimire

Vishnu Kotrajaras

B Klösgen

Other publications of authors with the same name

SOML Read: Rethinking the Read Operation Granularity of 3D NAND SSDs.C. Liu, J. Kotra, M. Jung, M. Kandemir, and C. Das. ASPLOS, page 955-969. ACM, (2019)Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling.J. Kotra, N. Shahidi, Z. Chishti, and M. Kandemir. ASPLOS, page 723-736. ACM, (2017)Eager Memory Cryptography in Caches.X. Wang, J. Kotra, and X. Jian. MICRO, page 693-709. IEEE, (2022)Athena: An Early-Fetch Architecture to Reduce on-Chip Page Walk Latencies.S. Vakil-Ghahani, S. Khadirsharbiyani, J. Kotra, and M. Kandemir. PACT, page 359-371. ACM, (2022)Quantifying the Potential Benefits of On-chip Near-Data Computing in Manycore Processors.J. Kotra, D. Guttman, N. Nachiappan, M. Kandemir, and C. Das. MASCOTS, page 198-209. IEEE Computer Society, (2017)CHAMELEON: A Dynamically Reconfigurable Heterogeneous Memory System.J. Kotra, H. Zhang, A. Alameldeen, C. Wilkerson, and M. Kandemir. MICRO, page 533-545. IEEE Computer Society, (2018)MDACache: Caching for Multi-Dimensional-Access Memories.S. George, M. Liao, H. Jiang, J. Kotra, M. Kandemir, J. Sampson, and V. Narayanan. MICRO, page 841-854. IEEE Computer Society, (2018)DSM: A Case for Hardware-Assisted Merging of DRAM Rows with Same Content.S. Vakil-Ghahani, M. Kandemir, and J. Kotra. SIGMETRICS (Abstracts), page 91-92. ACM, (2020)A Learning-Guided Hierarchical Approach for Biomedical Image Segmentation.H. Jiang, A. Sarma, J. Ryoo, J. Kotra, M. Arunachalam, C. Das, and M. Kandemir. SoCC, page 227-232. IEEE, (2018)Improving the Utilization of Micro-operation Caches in x86 Processors.J. Kotra, and J. Kalamatianos. MICRO, page 160-172. IEEE, (2020)

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Disambiguation of "Kotra, Jagadish B."

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Athena: An Early-Fetch Architecture to Reduce on-Chip Page Walk Latencies.

Please choose a person to relate this publication to

Jagadish Mudiganti

Jagadish Kulkarni

Jagadish Ghimire

Vishnu Kotrajaras

B Klösgen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kotra, Jagadish B."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Athena: An Early-Fetch Architecture to Reduce on-Chip Page Walk Latencies.

Please choose a person to relate this publication to

Jagadish Mudiganti

Jagadish Kulkarni

Jagadish Ghimire

Vishnu Kotrajaras

B Klösgen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Athena: An Early-Fetch Architecture to Reduce on-Chip Page Walk Latencies.