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Disambiguation of "Calazans, Ney Laert Vilar"

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ASCEnD-FreePDK45: An open source standard cell library for asynchronous design.

, , , and . ICECS, page 652-655. IEEE, (2016)

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Loreto Vilar

Ignazio Vilardi

Fabio Vilardi

Sisi Alexandra Vilardi

David Vilar Torres

 

Other publications of authors with the same name

NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (6): 1981-1993 (2018)Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes., , and . SBCCI, page 1-6. IEEE, (2012)Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique, , , , , and . CoRR, (2007)Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses., and . IEEE Trans. Educ., 44 (2): 109-119 (2001)Spatially Distributed Dual-Spacer Null Convention Logic Design., , , and . J. Low Power Electron., 10 (3): 313-320 (2014)Go functional model for a RISC-V asynchronous organisation - ARV., and . ICECS, page 381-384. IEEE, (2017)Design and Analysis of Testable Mutual Exclusion Elements., , , , , , and . ASYNC, page 124-131. IEEE Computer Society, (2015)Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications., , , , , and . ASYNC, page 11-18. IEEE Computer Society, (2016)Blade - A Timing Violation Resilient Asynchronous Template., , , , , , , , , and . ASYNC, page 21-28. IEEE Computer Society, (2015)A design flow for physical synthesis of digital cells with ASTRAN., , , , and . ACM Great Lakes Symposium on VLSI, page 245-246. ACM, (2014)