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Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (4): 683-693 (2017)H2B: Crypto Hash Functions Based on Hybrid Ring Generators., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (2): 442-455 (February 2024)High Volume Diagnosis in Memory BIST Based on Compressed Failure Data., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (3): 441-453 (2010)Ring generators - new devices for embedded test applications., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (9): 1306-1320 (2004)EDT Bandwidth Management in SoC Designs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (12): 1894-1907 (2012)Embedded deterministic test., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (5): 776-792 (2004)Hardware Protection via Logic Locking Test Points., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3020-3030 (2018)Logic BIST With Capture-Per-Clock Hybrid Test Points., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1028-1041 (2019)On necessary and nonconflicting assignments in algorithmic test pattern generation., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (4): 515-530 (1994)Low Cost Hypercompression of Test Data., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2964-2975 (2020)