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Fast parameters optimization of an iterative decoder using a configurable hardware accelerator., , , , , and . ISCAS (4), page 4159-4162. IEEE, (2005)High-voltage operational amplifier based on dual floating-gate transistors., , , and . ISCAS, IEEE, (2006)Spurs modeling in direct digital period synthesizers related to phase accumulator truncation., , and . ISCAS (3), page 389-392. IEEE, (2004)Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain., , , and . ISCAS, page 2559-2562. IEEE, (2014)Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector., and . ISCAS (4), page 369-372. IEEE, (2004)Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-Trees (TDFTs)., , , and . IEEE Access, (2019)Transport Triggered Polar Decoders., , , , and . ISTC, page 1-5. IEEE, (2018)Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories., , , and . NEWCAS, page 237-240. IEEE, (2017)A data driven CGRA Overlay Architecture with embedded processors., , and . NEWCAS, page 269-272. IEEE, (2017)A current-output DAC for low-power low-noise log-domain ΔΣ modulators., , and . NEWCAS, page 281-284. IEEE, (2014)