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Disambiguation of "Shi, Youhua"

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An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages.

, , , , and . VLSI-DAT, page 1-4. IEEE, (2013)

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Youhua Deng

Youhua Chen

Zhanjun Shi

Jian Shi

Renhu Shi

 

Other publications of authors with the same name

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit., , , and . APCCAS, page 607-610. IEEE, (2012)A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures., , , and . SoCC, page 7-12. IEEE, (2015)A delay variation and floorplan aware high-level synthesis algorithm with body biasing., , , and . ISQED, page 75-80. IEEE, (2016)Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow., , , and . IEEE Access, (2021)Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (9): 1063-1070 (2020)Timing monitoring paths selection for wide voltage IC., , , , and . IEICE Electron. Express, 13 (8): 20160095 (2016)MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures., , , and . IEICE Electron. Express, 9 (17): 1414-1422 (2012)A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists., , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2537-2546 (2015)An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (7): 1406-1418 (2015)An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (7): 1376-1391 (2015)