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Disambiguation of "Navabi, Zainalabedin"

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Utilizing Various ADL Facets for Instruction Level CPU Test.

, , , and . MTV, page 38-. IEEE Computer Society, (2003)

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Kambiz Navabi

Foroogh Navabi-Kermani

 

Other publications of authors with the same name

On-Chip Verification of NoCs Using Assertion Processors., , , , and . DSD, page 535-538. IEEE Computer Society, (2007)An off-line MDSI interconnect BIST incorporated in BS 1149.1., , , and . ETS, page 1-2. IEEE, (2014)SCOAP-based Directed Random Test Generation for Combinational Circuits., , , and . EWDTS, page 1-5. IEEE, (2019)An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements., , , , , , and . EWDTS, page 1-6. IEEE, (2019)Back-annotation of gate-level power properties into system level descriptions., and . NEWCAS, page 237-240. IEEE, (2014)A high-level language for design and modeling of hardware.. J. Syst. Softw., 18 (1): 5-18 (1992)Digital design and implementation with field programmable devices.. Kluwer, (2005)Programmable Routing Tables for Degradable Torus-Based Networks on Chips., , and . ISCAS, page 1065-1068. IEEE, (2007)An efficient BIST method for testing of embedded SRAMs., , and . ISCAS (5), page 73-76. IEEE, (2001)Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models., , , and . CHDL, volume A-32 of IFIP Transactions, page 569-586. North-Holland, (1993)