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Variability Influence on FinFET-Based On-Chip Memory Data Paths.

, , , and . J. Low Power Electron., 11 (2): 250-255 (2015)

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All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator., , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (2): 90-94 (2014)Optimization of FinFET-Based Gain Cells for Low Power Sub-V T Embedded DRAMs., , , and . J. Low Power Electron., 14 (2): 236-243 (2018)Novel redundant logic design for noisy low voltage scenarios., , , and . LASCAS, page 1-4. IEEE, (2013)High level spectral-based analysis of power consumption in DSPs systems., , and . ISCAS, IEEE, (2006)Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact., , , and . IEEE Access, (2022)Feasibility of Embedded DRAM Cells on FinFET Technology., , , , and . IEEE Trans. Computers, 65 (4): 1068-1074 (2016)New redundant logic design concept for high noise and low voltage scenarios., , , , , and . Microelectron. J., 42 (12): 1359-1369 (2011)Selective Clock-Gating for Low-Power Synchronous Counters., , and . J. Low Power Electron., 1 (3): 217-225 (2005)Two examples of approximate arithmetic to reduce hardware complexity and power consumption., , , , , , , , and . DCIS, page 1-6. IEEE, (2022)PVTA Tolerant Self-adaptive Clock Generation Architecture., , and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 142-154. Springer, (2012)