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Disambiguation of "Egawa, Ryusuke"

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Design and evaluation of a media-oriented vector processor with a multi-banked cache memory.

, , , , and . ESTIMedia, page 78-87. IEEE, (2013)

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Ryusuke Shimada

Masashi Egawa

Yuko Egawa

Kazuko Pfeiffer-Egawa

 

Other publications of authors with the same name

A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers., , , , and . 3DIC, page 1-6. IEEE, (2011)Vertically integrated processor and memory module design for vector supercomputers., , , and . 3DIC, page 1-6. IEEE, (2013)A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts., , , and . IEICE Trans. Inf. Syst., 96-D (9): 2047-2054 (2013)OpenCL-like offloading with metaprogramming for SX-Aurora TSUBASA., , , and . Parallel Comput., (2021)Improving Quantum Annealing Performance on Embedded Problems., , , and . Supercomput. Front. Innov., 7 (4): 32-48 (2020)An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches., , , , and . IEEE Trans. Multi Scale Comput. Syst., 4 (4): 593-604 (2018)An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches., , , and . COOL Chips, page 1-2. IEEE Computer Society, (2017)An energy-efficient dynamic memory address mapping mechanism., , , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2015)Cache partitioning strategies for 3-D stacked vector processors., , , and . 3DIC, page 1-6. IEEE, (2010)Automatically Avoiding Memory Access Conflicts on SX-Aurora TSUBASA., , , , and . IPDPS Workshops, page 822-829. IEEE, (2020)