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A clustered VLIW architecture based on queue register files.. University of Edinburgh, UK, (1998)British Library, EThOS.Automatic Generation of Custom Parallel Processors for Morphological Image Processing., and . SBAC-PAD, page 176-181. IEEE Computer Society, (2014)Poster: A Software Framework for Easy Integration of Speech Recognition into 3D Browsers., , and . 3DUI, page 151-152. IEEE Computer Society, (2008)CHAOS-MCAPI: An Optimized Mechanism to Support Multicore Parallel Programming., , and . SBAC-PAD (Workshops), page 85-90. IEEE Computer Society, (2015)From MultiTask to MultiCore: Design and Implementation Using an RTOS., , , and . ISPDC, page 111-118. IEEE, (2014)Analytical Performance Modelling of the CPER Multiprocessor., and . PDPTA, page 1409-1420. CSREA Press, (1996)ARCHITECT-R: A System for Reconfigurable Robots Design., , , , , , and . SAC, page 679-683. ACM, (2003)Allocating Lifetimes to Queues in Software Pipelined Architectures., , and . Euro-Par, volume 1300 of Lecture Notes in Computer Science, page 1066-1073. Springer, (1997)Distributed Modulo Scheduling., , and . HPCA, page 130-134. IEEE Computer Society, (1999)Partitioned Schedules for Clustered VLIW Architectures., , and . IPPS/SPDP, page 386-391. IEEE Computer Society, (1998)