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On wirelength estimations for row-based placement., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1265-1278 (1999)Optimal partitioners and end-case placers for standard-cell layout., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (11): 1304-1313 (2000)Synthesis of reversible logic circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 710-722 (2003)Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (12): 2107-2119 (2008)Faster Schrödinger-style simulation of quantum circuits., and . CoRR, (2020)Large-scale Boolean matching., and . DATE, page 771-776. IEEE Computer Society, (2010)Customizing IP cores for system-on-chip designs using extensive external don't-cares., , and . DATE, page 582-585. IEEE, (2009)Synthesis of quantum logic circuits., , and . ASP-DAC, page 272-275. ACM Press, (2005)On wirelength estimations for row-based placement., , , , and . ISPD, page 4-11. ACM, (1998)Faster minimization of linear wirelength for global placement., , , , , , and . ISPD, page 4-11. ACM, (1997)