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Address Translation Optimization for Unified Parallel C Multi-dimensional Arrays.

, , , , and . IPDPS Workshops, page 1191-1198. IEEE, (2011)

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Efficient cache design for solid-state drives., , , , and . Conf. Computing Frontiers, page 41-50. ACM, (2010)Enabling PGAS Productivity with Hardware Support for Shared Address Mapping: A UPC Case Study., , , and . HPCC/CSS/ICESS, page 1-10. IEEE, (2014)COnfigurable Network Protocol Accelerator (COPA) † : An Integrated Networking/Accelerator Hardware/Software Framework., , and . Hot Interconnects, page 17-24. IEEE, (2020)Configurable Network Protocol Accelerator (COPA)., , and . IEEE Micro, 41 (1): 8-14 (2021)Bandwidth Adaptive Write-update Optimizations for Chip Multiprocessors., , and . ISPA, page 199-206. IEEE Computer Society, (2012)Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study., , , and . Int. J. Reconfigurable Comput., (2010)Hardware Support for Address Mapping in PGAS Languages; a UPC Case Study., , , and . CoRR, (2013)Adaptive Cache Coherence Mechanisms with Producer-Consumer Sharing Optimization for Chip Multiprocessors., , and . IEEE Trans. Computers, 64 (2): 316-328 (2015)Address Translation Optimization for Unified Parallel C Multi-dimensional Arrays., , , , and . IPDPS Workshops, page 1191-1198. IEEE, (2011)Where should the threads go? Leveraging hierarchical data locality to solve the thread affinity dilemma., , , and . ICPADS, page 384-391. IEEE Computer Society, (2014)