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Address Translation Optimization for Unified Parallel C Multi-dimensional Arrays.

, , , , and . IPDPS Workshops, page 1191-1198. IEEE, (2011)

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Bandwidth Adaptive Cache Coherence Optimizations for Chip Multiprocessors., , and . Int. J. Parallel Program., 42 (3): 435-455 (2014)Improving Efficiency in Large-Scale Decentralized Distributed Training., , , , , , , , , and 2 other author(s). ICASSP, page 3022-3026. IEEE, (2020)Hardware support for address mapping in PGAS languages: a UPC case study., , , and . Conf. Computing Frontiers, page 22:1-22:2. ACM, (2014)Performance analysis and tuning for clusters with ccNUMA nodes for scientific coputing - a case study., , , , and . Comput. Syst. Sci. Eng., (2009)Experimental Evaluation of Emerging Multi-core Architectures., , , and . IPDPS, page 1-6. IEEE, (2007)Hardware Support for Address Mapping in PGAS Languages; a UPC Case Study., , , and . CoRR, (2013)An adaptive cache coherence protocol for chip multiprocessors., and . IFMT, page 4:1-4:10. ACM, (2010)Comparing Runtime Systems with Exascale Ambitions Using the Parallel Research Kernels., , , , , , , , and . ISC, volume 9697 of Lecture Notes in Computer Science, page 321-339. Springer, (2016)Adaptive Cache Coherence Mechanisms with Producer-Consumer Sharing Optimization for Chip Multiprocessors., , and . IEEE Trans. Computers, 64 (2): 316-328 (2015)Address Translation Optimization for Unified Parallel C Multi-dimensional Arrays., , , , and . IPDPS Workshops, page 1191-1198. IEEE, (2011)