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Disambiguation of "Asada, Kunihiro"

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A Structural Approach for Transistor Circuit Synthesis.

, , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3529-3537 (2006)

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Kunihiro Jojima

 

Other publications of authors with the same name

A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation., , and . IEEE J. Solid State Circuits, 46 (11): 2500-2513 (2011)One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects., , and . VLSI Design, 6 (1-4): 65-67 (1998)A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary., , and . ISSCC, page 404-405. IEEE, (2010)Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA., , and . ISLPED, page 3-8. IEEE/ACM, (2011)One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise., , , and . EWME, page 1-3. IEEE, (2016)Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3485-3491 (2005)A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging., , and . IEICE Trans. Electron., 94-C (10): 1626-1633 (2011)All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter., , , , and . IEICE Trans. Electron., 94-C (4): 487-494 (2011)Autonomous di/dt Control of Power Supply for Margin Aware Operation., , and . IEICE Trans. Electron., 89-C (11): 1689-1694 (2006)A CMOS Broadband Transceiver with On-Chip Antenna Array and Built-In Pulse-Delay Calibration for Millimeter-Wave Imaging Applications., and . IEICE Trans. Electron., 100-C (12): 1078-1086 (2017)