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Testbench Qualification of SystemC TLM Protocols through Mutation Analysis., , , and . IEEE Trans. Computers, 63 (5): 1248-1261 (2014)A SystemC-based platform for assertion-based verification and mutation analysis in systems biology., , , , , , and . LATS, page 159-164. IEEE, (2016)A fault tolerant incremental design methodology., , and . ISCAS (3), page 161-164. IEEE, (2002)Code Manipulation for Virtual Platform Integration., , and . IEEE Trans. Computers, 65 (9): 2694-2708 (2016)Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques., , , , and . DAC, page 467-470. ACM Press, (1996)An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems, , , , , , and . CoRR, (2007)On the automatic synthesis of parallel SW from RTL models of hardware IPs., , , and . ACM Great Lakes Symposium on VLSI, page 71-74. ACM, (2012)A timing-accurate modeling and simulation environment for networked embedded systems., , , , , and . DAC, page 42-47. ACM, (2003)Abstraction of RTL IPs into embedded software., , and . DAC, page 24-29. ACM, (2010)A design methodology for the correct specification of VLSI systems., , , , , and . Microprocess. Microprogramming, 38 (1-5): 563-570 (1993)