@article{journals/corr/abs-2310-14049,
added-at = {2023-10-27T00:00:00.000+0200},
author = {Gao, Xiaohan and Zhang, Haoyi and Ye, Siyuan and Liu, Mingjie and Pan, David Z. and Shen, Linxiao and Wang, Runsheng and Lin, Yibo and Huang, Ru},
biburl = {https://www.bibsonomy.org/bibtex/2c99cea3e4077efe7a9268fdc1f9613c7/dblp},
ee = {https://doi.org/10.48550/arXiv.2310.14049},
interhash = {282dfa7d6a61ddd0c467e8f6a269da41},
intrahash = {c99cea3e4077efe7a9268fdc1f9613c7},
journal = {CoRR},
keywords = {dblp},
timestamp = {2024-04-09T00:04:04.000+0200},
title = {Post-Layout Simulation Driven Analog Circuit Sizing.},
url = {http://dblp.uni-trier.de/db/journals/corr/corr2310.html#abs-2310-14049},
volume = {abs/2310.14049},
year = 2023
}