%0 Journal Article %1 journals/jssc/NodaTMIMKIANITH01 %A Noda, Kenji %A Takeda, Koichi %A Matsui, Koujirou %A Ito, Shinya %A Masuoka, Sadaaki %A Kawamoto, Hideaki %A Ikezawa, Nobuyuki %A Aimoto, Yoshiharu %A Nakamura, Noritsugu %A Iwasaki, Takahiro %A Toyoshima, Hideo %A Horiuchi, Tadahiko %D 2001 %J IEEE J. Solid State Circuits %K dblp %N 3 %P 510-515 %T An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. %U http://dblp.uni-trier.de/db/journals/jssc/jssc36.html#NodaTMIMKIANITH01 %V 36

@article{journals/jssc/NodaTMIMKIANITH01, added-at = {2022-04-04T00:00:00.000+0200}, author = {Noda, Kenji and Takeda, Koichi and Matsui, Koujirou and Ito, Shinya and Masuoka, Sadaaki and Kawamoto, Hideaki and Ikezawa, Nobuyuki and Aimoto, Yoshiharu and Nakamura, Noritsugu and Iwasaki, Takahiro and Toyoshima, Hideo and Horiuchi, Tadahiko}, biburl = {https://www.bibsonomy.org/bibtex/28ebf4075ec7eb2fd6609ca1ec73147be/dblp}, ee = {https://doi.org/10.1109/4.910490}, interhash = {2cbf242cf01d29e3cf5c096ae9e51b94}, intrahash = {8ebf4075ec7eb2fd6609ca1ec73147be}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 3, pages = {510-515}, timestamp = {2024-04-08T10:44:03.000+0200}, title = {An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc36.html#NodaTMIMKIANITH01}, volume = 36, year = 2001 }