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Disambiguation of "Aimoto, Yoshiharu"

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An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 36 (3): 510-515 (2001)

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Yoshiharu Kasai

Yoshiharu Krockenberger

 

Other publications of authors with the same name

A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM., , , , , , , and . IEEE J. Solid State Circuits, 29 (11): 1336-1343 (November 1994)An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration., , , , and . FCCM, page 264-266. IEEE Computer Society, (1998)An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 36 (3): 510-515 (2001)A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications., , , , , , and . IEEE J. Solid State Circuits, 41 (1): 113-121 (2006)Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs., , , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 806-814 (2011)Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications., , , , , , , and . IEEE J. Solid State Circuits, 30 (6): 637-643 (June 1995)Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes., , , , , and . IEEE J. Solid State Circuits, 41 (4): 805-814 (2006)A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 35 (11): 1631-1640 (2000)An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield., , , , , , , , , and 2 other author(s). CICC, page 283-286. IEEE, (2000)