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Disambiguation of "Nakamura, Noritsugu"

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An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 36 (3): 510-515 (2001)

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Shin'ichiro Nakamura

Makoto Nakamura

Akira Nakamura

Hideki Nakamura

Hatsuo Nakamura

 

Other publications of authors with the same name

High-level synthesis challenges and solutions for a dynamically reconfigurable processor., , , , , and . ICCAD, page 702-708. ACM, (2006)Constructing a Human-like agent for the Werewolf Game using a psychological model based multiple perspectives., , , , , , and . SSCI, page 1-8. IEEE, (2016)Optimizing time and space multiplexed computation in a dynamically reconfigurable processor., , , , , , and . FPT, page 106-111. IEEE, (2013)A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 35 (11): 1631-1640 (2000)High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor., , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 36 (3): 510-515 (2001)New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications., , , , , , , , and . VLSI Circuits, page 41-42. IEEE, (2018)